Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter
By: Jalaja, S
.
Contributor(s): Vijaya Prakash, A. M.
Publisher: New Delhi STM Journals 2018Edition: Vol,8(3), Sep-Dec.Description: 1-9p.Subject(s): EXTC EngineeringOnline resources: Click Here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art research architecture. This retiming adaptive filter architecture improves the system performance of the design. Using 90 nm technology, node power analysis is done for 8-bit input sample with different tap lengths. Synthesis results show that the retimed adaptive filter mechanism achieves an average of 82.9 and 82.6% less power consumption for the input sample of 8 and 16-bit respectively compared to existing result. The physical design for 16-bit input data with 24 tap length, LMS filter architecture is implemented using 45 nm CMOS technology. Effectiveness of retime version of LMS model experimental result shows better performance in terms power consumption.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
Articles Abstract Database
|
School of Engineering & Technology Archieval Section | Not for loan | 2021-2021714 |
Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art research architecture. This retiming adaptive filter architecture improves the system performance of the design. Using 90 nm technology, node power analysis is done for 8-bit input sample with different tap lengths. Synthesis results show that the retimed adaptive filter mechanism achieves an average of 82.9 and 82.6% less power consumption for the input sample of 8 and 16-bit respectively compared to existing result. The physical design for 16-bit input data with 24 tap length, LMS filter architecture is implemented using 45 nm CMOS technology. Effectiveness of retime version of LMS model experimental result shows better performance in terms power consumption.
Click on an image to view it in the image viewer
There are no comments for this item.